The escalating requirements for high densification and performance associated with ultra large scale integration semiconductor devices requires design features of 0.375.mu. and under, such as 0.25.mu. and under, increased transistor and circuit speeds, high reliability and increased manufacturing throughput for competitiveness. The reduction of design features to 0.357.mu. and under generates numerous problems challenging the limitations of conventional semiconductor manufacturing technology.
Conventional semiconductor devices comprise a substrate and various electrically isolated regions, or so called active regions, in which individual circuit components are formed. The electrical isolation of these active regions is typically accomplished by thermal oxidation of the semiconductor substrate, typically monocrystalline silicon or an epitaxial layer formed thereon, bounding the active regions. The conventional method for forming a field oxide comprises growing or depositing an oxide layer on a semiconductor substrate and depositing a nitride layer thereon. The oxide and nitride layers are patterned employing conventional photolithographic and etching techniques to form a masking layer having openings extending down to and exposing the underlying substrate. The openings define areas on the surface of the substrate in which field oxide regions are subsequently formed. These exposed regions are commonly referred to as the "field."
The field oxide regions are formed by heating the substrate with the field regions exposed to an oxidizing gas, such as oxygen, i.e., a technique known as Local Oxidation of Silicon (LOCOS). Often, an ion implantation step is performed prior to oxidation to ensure the proper functioning of the individually isolated circuit elements in the active regions. Subsequent to oxidation, the nitride layer is removed by some combination of chemical and/or physical etching. LOCOS methodology disadvantageously results in the formation of a field oxide region having edges which taper in its vertical dimension both above and below the original surface of the semiconductor substrate. This tapering end portion resembles and, therefore, is commonly referred to as, a "bird's beak." The bird's beak is formed during the thermal oxidation of the field regions because the oxygen which diffuses vertically into the substrates in the open areas also diffuses horizontally once it has penetrated the substrate.
LOCOS methodology is attendant with several inherent problems. For example, while the horizontal extent of the bird's beak can be loosely controlled by the stress induced in the masking layers adjacent to the field, this same stress can cause strain defects in the active areas including point defects, dislocations, stacking faults, as well as catastrophic failures such as delamination, particle generation, etc. In addition, the extent to which stress/encroachment can be controlled is dependent upon the initial thickness and intrinsic/extrinsic stress condition of the masking layers. Thus the system is complicated and difficult to control with high uniformity. Moreover, the aggressive scaling of gate electrode dimensions into the deep submicron regime, such as less than about 0.375 .mu., requires tighter source/drain region to source/drain region spacing which is adversely affected by the bird's beak attendant upon LOCOS methodology.
Another type of isolation structure is known as trench isolation. A trench isolation structure is quite distinct from a field oxide region in structure and the manner in which it is formed. Typically, a pad oxide layer, e.g., silicon dioxide, is formed on a surface of a semiconductor substrate or on a surface of an epitaxial layer formed on the semiconductor substrate. A nitride layer, such as silicon nitride, is formed on the pad oxide layer and a mask is provided on the nitride layer having an opening therein. Anisotropic etching is then conducted to remove portions of the underlying nitride and pad oxide layers and form a trench in the substrate or epitaxial layer, which trench has edges at the surface of the substrate or epitaxial layer. After trench formation, an oxide liner is typically thermally grown in the trench and on the trench edges to control the silicon-silicon dioxide interface quality. The trench is then refilled with an insulating material, such as silicon dioxide derived from tetraethyl orthosilicate (TEOS) and deposited by low pressure chemical vapor deposition (LPCVD). The surface is then planarized, as by chemical-mechanical polishing (CMP), to complete the trench isolation structure. Subsequent to CMP, the silicon nitride layer is removed. Typically, a retrograde well structure is formed by ion implantation with subsequent heating to densify the TEOS derived oxide trench fill and to activate the retrograde well implants. Such a densification-activation heating step is generally conducted at about 900.degree. C. to about 1,100.degree. C. for about 2 hours to about 3 hours.
The remaining portion of the pad oxide layer is then removed with dilute hydrofluoric acid (HF), followed by an industrial standard "RCA" clean. A high quality gate oxide having a thickness of about 30 .ANG. to about 50 .ANG. is grown followed by polysilicon deposition. The weakest part of the gate oxide is at the trench edges. Moreover, defects in the underlying surface appear to concentrate in clusters at the trench edges. Disadvantageous parasitic transistors are formed at the trench edges. Such parasitic edge transistors turn on at a lower voltage than the active device, thereby causing a phenomenon characterized as a "subthreshold kink" in the current-voltage (I-V) characteristic curve of the transistor. Moreover, the gate oxide layer is disadvantageously thinned at the trench edges, with an attendant increase in the electric field strength at the trench edges and decrease in device reliability. As the design rule shrinks to 0.375.mu. and under, particularly to 0.25.mu. and under, the adverse consequences of trench edges are exacerbated.
There exists a continuing need for shallow trench isolation methodology, wherein the resulting gate oxide layer at the trench edges exhibits high reliability. There exists a particular continuing need for shallow trench isolation methodology for semiconductor devices having a design rule of about 0.375.mu. and under, wherein an ultra thin gate oxide having high integrity is formed at the trench edges.